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19-1088; Rev 3; 12/99
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
General Description
The MAX544/MAX545 are serial-input, voltage-output, 14-bit digital-to-analog converters (DACs) that operate from a single +5V supply. They provide 14-bit performance (0.5LSB INL and 0.9LSB DNL) over temperature without any adjustments. The DAC output is unbuffered, resulting in a low supply current of 0.3mA and a low offset error of 0.6mV. The DAC output range is 0V to VREF. For bipolar operation, matched scaling resistors are provided in the MAX545 for use with an external precision op amp (such as the MAX400), generating a V REF output swing. The MAX545 also includes Kelvin-sense connections for the reference and analog ground pins to reduce layout sensitivity. A 16-bit serial word is used to load data into the DAC latch. The 10MHz, 3-wire serial interface is compatible with SPITM/QSPITM/MICROWIRETM, and it also interfaces directly with optocouplers for applications requiring isolation. A power-on reset circuit clears the DAC output to 0V (unipolar mode) when power is initially applied. The MAX544 is available in 8-pin plastic DIP and SO packages. The MAX545 is available in 14-pin plastic DIP and SO packages. o +5V Single-Supply Operation o Low Power: 1.5mW o 1s Settling Time o Unbuffered Voltage Output Directly Drives 60k Loads o SPI/QSPI/MICROWIRE-Compatible Serial Interface o Power-On Reset Circuit Clears DAC Output to 0V (unipolar mode) o Schmitt-Trigger Inputs for Direct Optocoupler Interface o Pin-Compatible 16-Bit Upgrades (MAX541/MAX542)
Features
o Full 14-Bit Performance Without Adjustments
MAX544/MAX545
Ordering Information
PART MAX544ACPA MAX544BCPA MAX544ACSA MAX544BCSA TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO INL (LSB) 1/2 1 1/2 1
Applications
Digital Offset and Gain Adjustment Instrumentation Industrial Process Control Automated Test Equipment Data-Acquisition Systems
Ordering Information continued at end of data sheet.
Functional Diagrams
VDD RFB RFB INV
Pin Configurations
TOP VIEW
REFF REFS
MAX545
RINV
RFB 1 OUT 2 14 VDD 13 INV
14-BIT DAC
OUT AGNDF
OUT 1 AGND 2 REF 3 CS 4
8 VDD
AGNDF 3 AGNDS 4 REFS 5
MAX545
12 DGND 11 LDAC 10 DIN 9 N.C. 8 SCLK
MAX544
7 DGND 6 DIN 5 SCLK
REFF 6 CS 7
CS LDAC SCLK DIN
DATA LATCH CONTROL LOGIC SERIAL INPUT REGISTER DGND
AGNDS
DIP/SO
DIP/SO
Functional Diagrams continued at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
ABSOLUTE MAXIMUM RATINGS
VDD to DGND ...........................................................-0.3V to +6V CS, SCLK, DIN, LDAC to DGND ..............................-0.3V to +6V REF, REFF, REFS to AGND ........................-0.3V to (VDD + 0.3V) AGND, AGNDF, AGNDS to DGND .......................-0.3V to +0.3V OUT, INV to AGND DGND .......................................-0.3V to VDD RFB to AGND DGND...................................................-6V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.09mW/C above +70C) .....727mW 8-Pin SO (derate 5.88mW/C above +70C) .................471mW 14-Pin Plastic DIP (derate 10.00mW/C above +70C) ...800mW 14-Pin SO (derate 8.33mW/C above +70C) ...............667mW 14-Pin Ceramic SB (derate 10.00mW/C above +70C...800mW Operating Temperature Ranges MAX544 _C_ A/MAX545_C_D ..............................0C to +70C MAX544 _E_ A/MAX545_E_D............................-40C to +85C MAX545BMJD .................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN 14 MAX54_A MAX54_B 0.15 0.15 0.15 0.05 5 0.1 ROUT (Note 2) MAX545 MAX545 BZSTC PSR VREF RREF MAX545 4.75V VDD 5.25V (Note 3) Unipolar mode MAX545, bipolar mode 2.0 11.5 9.0 25 1 10 10 0.5 1.0 3.0 RFB/RINV Ratio error 6.25 1.0 0.03 10 0.5 1 0.9 0.6 TYP MAX UNITS Bits LSB LSB mV ppm/C LSB ppm/C k STATIC PERFORMANCE--ANALOG SECTION (RL = ) Resolution N Integral Nonlinearity Differential Nonlinearity Zero-Code Offset Error Zero-Code Tempco Gain Error (Note 1) Gain-Error Tempco DAC Output Resistance Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Tempco Power-Supply Rejection REFERENCE INPUT Reference Input Range Reference Input Resistance (Note 4) INL DNL ZSE ZSTC VDD = 5V Guaranteed monotonic
%
LSB ppm/C LSB V k
DYNAMIC PERFORMANCE--ANALOG SECTION (RL = , unipolar mode) Voltage-Output Slew Rate SR CL = 10pF (Note 5) Output Settling Time DAC Glitch Impulse Digital Feedthrough To /2LSB of FS, CL = 10pF Major-carry transition Code = 0000 hex; CS = VDD; LDAC = 0V; SCLK, DIN = 0V to VDD levels
1
V/s s nVs nVs
2
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance SNR CIN Code = 0000 hex Code = FFFC hex 2.4 0.8 VIN = 0 (Note 6) 0.40 4.75 0.3 1.5 5.25 1.1 1 10 SYMBOL BW CONDITIONS Code = FFFC hex Code = 0000 hex, VREF = 1Vp-p at 100kHz MIN TYP 1 1 83 75 120 MAX UNITS MHz mVp-p dB pF
MAX544/MAX545
DYNAMIC PERFORMANCE--REFERENCE SECTION
STATIC PERFORMANCE--DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance Hysteresis Voltage POWER SUPPLY Positive Supply Range Positive Supply Current Power Dissipation VDD IDD PD V mA mW VIH VIL IIN CIN VH V V A pF V
TIMING CHARACTERISTICS
(VDD = +5V 5%, VREF = +2.5V, AGND = DGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Frequency SCLK Pulse Width High SCLK Pulse Width Low CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold LDAC Pulse Width CS High to LDAC Low Setup VDD High to CS Low (power-up delay) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: SYMBOL fSCLK tCH tCL tCSS0 tCSS1 tCSH0 tCSH1 tDS tDH tLDAC tLDACS MAX545 MAX545 (Note 6) (Note 6) 45 45 45 45 30 45 40 0 50 50 20 CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns s
Gain Error tested at VREF = 2.0V, 2.5V, and 3.0V. ROUT tolerance is typically 20%. Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance. Reference input resistance is code dependent, minimum at 8554 hex. Slew-rate value is measured from 0% to 63%. Guaranteed by design. Not production tested.
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
Typical Operating Characteristics
(VDD = 5V, VREF = +2.5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX544/MAX545-01
SUPPLY CURRENT vs. REFERENCE VOLTAGE
MAX544/MAX545-02
ZERO-CODE OFFSET ERROR vs. TEMPERATURE
0.15 ZERO-CODE OFFSET ERROR (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
MAX544/MAX545-03
0.50 0.45 SUPPLY CURRENT (mA) 0.40 0.35 0.30 0.25 0.20 -40 -20 0 20 40 60 80
0.35 0.34 0.33 SUPPLY CURRENT (mA) 0.32 0.31 0.30 0.29 0.28 0.27 0.26 0.25
0.20
100
0
1
2
3
4
5
6
-60
-20
20
60
100
140
TEMPERATURE (C)
REFERENCE VOLTAGE (V)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX544/MAX545-04
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX544/MAX545-05
GAIN ERROR vs. TEMPERATURE
0.15 0.10
MAX544/MAX545-06
0.30 0.20 0.10 INL (LSB) 0 -0.10 -0.20 -0.30 -60 -20 20 60 100 -INL
0.30 0.20 0.10 DNL (LSB) 0 -DNL -0.10 -0.20 -0.30
0.20
+INL
+DNL
GAIN ERROR (LSB)
0.05 0 -0.05 -0.10 -0.15 -0.20
140
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. CODE
MAX544/MAX545-07
DIFFERENTIAL NONLINEARITY vs. CODE
MAX544/MAX545-08
REFERENCE CURRENT vs. CODE
MAX544/MAX545-09
0.250
0.250
200
REFERENCE CURRENT (A) 0
0.125 DNL (LSB) INL (LSB)
0.125
160
120
0
0
80
-0.125
-0.125
40
-0.250 0 5k 10k DAC CODE 15k 20k
-0.250 5k 10k DAC CODE 15k 20k
0 0 4k 8k 12k 16k 20k DAC CODE
4
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = +2.5V, TA = +25C, unless otherwise noted.) FULL-SCALE STEP RESPONSE (fSCLK = 10MHz)
MAX544-10
MAX544/MAX545
FULL-SCALE STEP RESPONSE (fSCLK = 20MHz)
CL = 10pF RL =
MAX544-10A
CL = 10pF RL =
OUT 500mV/div
OUT 500mV/div
2s/div 1s/div
2s/div 400ns/div
MAJOR-CARRY OUTPUT GLITCH
DIGITAL FEEDTHROUGH
CS (5V/div)
SCLK 5V/div
OUT (AC-COUPLED, 100mV/div) 2s/div
MAX544/MAX545-11
OUT (AC-COUPLED, 50mV/div) 2s/div
MAX544/MAX545-12
CODE = 0000 hex
Pin Descriptions
MAX544
PIN 1 2 3 4 5 6 7 8 NAME OUT AGND REF CS SCLK DIN DGND VDD DAC Output Voltage Analog Ground Voltage Reference Input. Connect to external +2.5V reference. Chip-Select Input Serial-Clock Input. Duty cycle must be between 40% and 60%. Serial-Data Input Digital Ground +5V Supply Voltage 5 FUNCTION
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
Pin Descriptions (continued)
MAX545
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME RFB OUT AGNDF AGNDS REFS REFF CS SCLK N.C. DIN LDAC DGND INV VDD FUNCTION Feedback Resistor. Connect to external op amp's output in bipolar mode. DAC Output Voltage Analog Ground (force) Analog Ground (sense) Voltage Reference Input (sense). Connect REFS to external +2.5V reference. Voltage Reference Input (force). Connect REFF to external +2.5V reference. Chip-Select Input Serial-Clock Input. Duty cycle must be between 40% and 60%. No Connection. Not internally connected. Serial-Data Input LDAC Input. A falling edge updates the internal DAC latch. Digital Ground Junction of internal scaling resistors. Connect to external op amp's inverting input in bipolar mode. +5V Supply Voltage
;;;;;;;; ;;;;;;;;;
tCSH1 tLDACS CS tCSHO tCSSO tCH tCL tCSS1 SCLK tDH tDS DIN D13 D12 S0 LDAC* tLDAC *MAX545 ONLY
Figure 1. Timing Diagram
6
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
+5V +2.5V 10F
0.1F 0.1F
MC68XXXX
PCS0 MOSI SCLK (GND) CS DIN SCLK
VDD
REF (REFF)
(REFS) UNIPOLAR OUT
MAX495
MAX544/MAX545
OUT
EXTERNAL OP AMP
(LDAC)
DGND
AGND_
( ) ARE FOR MAX545 ONLY
Figure 2a. Typical Operating Circuit--Unipolar Output
+5V +2.5V
10F
0.1F 0.1F +5V
MC68XXXX
PCS0 MOSI SCLK IC1 (GND) CS DIN
VDD
REFF
REFS RINV RFB
RFB INV MAX400 OUT BIPOLAR OUT EXTERNAL OP AMP
SCLK LDAC DGND
MAX545
-5V AGNDF AGNDS
Figure 2b. Typical Operating Circuit--Bipolar Output
Detailed Description
The MAX544/MAX545 voltage-output, 14-bit digital-toanalog converters (DACs) offer full 14-bit performance with less than 0.5LSB integral linearity error and less than 0.9LSB differential linearity error, thus ensuring monotonic performance. Serial-data transfer minimizes the number of package pins required. The MAX544/MAX545 are composed of two matched DAC sections, with an inverted R-2R DAC forming the LSBs and the four MSBs derived from 15 identically matched resistors. This architecture allows the lowest glitch energy to be transferred to the DAC output on
major-carry transitions. It also lowers the DAC output impedance by a factor of eight compared to a standard R-2R ladder, allowing unbuffered operation in mediumload applications. The MAX545 provides matched bipolar offset resistors, which connect to an external op amp for bipolar output swings (Figure 2b). For optimum performance, the MAX545 also provides a set of Kelvin connections to the voltage-reference and analog-ground inputs.
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7
+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
Digital Interface
The MAX544/MAX545's digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE interfaces. The chip-select input (CS) frames the serial data loading at the data-input pin (DIN). Immediately following CS's high-to-low transition, the data is shifted synchronously and latched into the input register on the rising edge of the serial clock input (SCLK). After 16 bits (14 data bits, plus 2 sub-bits set to zero) have been loaded into the serial input register, it transfers its contents to the DAC latch on CS's low-tohigh transition (Figure 3a). Note that if CS is not kept low during the entire 16 SCLK cycles, data will be corrupted. In this case, reload the DAC latch with a new 16-bit word. Alternatively, for the MAX545, LDAC allows the DAC latch to update asynchronously by pulling LDAC low after CS goes high (Figure 3b). Hold LDAC high during the data-loading sequence.
External Reference
The MAX544/MAX545 operate with external voltage references from 2V to 3V. The reference voltage determines the DAC's full-scale output voltage. Kelvin connections are provided with the MAX545 for optimum performance. The 2.5V MAX873A, with 15mV initial accuracy and a 7ppm/C (max) temperature coefficient, is a good choice.
Power-On Reset
The MAX544/MAX545 have a power-on reset circuit to set the DAC's output to 0V in unipolar mode when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system power-up, such as after a loss of power. In bipolar mode, the DAC output is set to -VREF.
Figure 3a. MAX544/MAX545 3-Wire Interface Timing Diagram (LDAC = DGND for MAX545)
SCLK
LDAC
; ; ;; ;;; ;;;
CS DAC UPDATED SCLK SUB-BITS DIN D13 D12 D11 D10 D9 D8 D7 D6 MSB D5 D4 D3 D2 D1 D0 S1 S0 LSB CS SUB-BITS DIN D13 D12 D11 D10 D9 D8 D7 D6 MSB D5 D4 D3 D2 D1 D0 S1 S0 LSB DAC UPDATED
Figure 3b. MAX545 4-Wire Interface Timing Diagram
8
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs
Applications Information
Reference and Analog Ground Inputs
The MAX544/MAX545 operate with external voltage references from 2V to 3V, and maintain 14-bit performance if certain guidelines are followed when selecting and applying the reference. Ideally, the reference's temperature coefficient should be less than 1.5ppm/C to maintain 14-bit accuracy to within 1LSB over the 0C to +70C commercial temperature range. Since this converter is designed as an inverted R-2R voltage-mode DAC, the input resistance seen by the voltage reference is code dependent. The worst-case input-resistance variation is from 11.5k (at code 8554 hex) to 200k (at code 0000 hex). The maximum change in load current for a +2.5V reference is +2.5V / 11.5k = 217A; therefore, the required load regulation is 28ppm/mA for a maximum error of 0.1LSB. This implies a reference output impedance of less than 71m. In addition, the signal-path impedance from the voltage reference to the reference input must be kept low because it contributes directly to the load-regulation error. The requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. A 0.1F ceramic capacitor with short leads between REFF and AGNDF (MAX545), or REF and AGND (MAX544), provides high-frequency bypassing. A surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. An additional 10F between REFF and AGNDF (MAX545), or REF and AGND (MAX544), provides low-frequency bypassing. A low-ESR tantalum, film, or organic semiconductor capacitor works well. Leaded capacitors are acceptable because impedance is not as critical at lower frequencies. The circuit can benefit from even larger bypassing capacitors, depending on the stability of the external reference with capacitive loading. If separate force and sense lines are not used, tie the appropriate force and sense pins together close to the package. AGND must also be low impedance, as load-regulation errors will be introduced by excessive AGND resistance. As in all high-resolution, high-accuracy applications, separate analog and digital ground planes yield the best results. Tie DGND to AGND at the AGND pin to form the "star" ground for the DAC system. Always refer remote DAC loads to this system ground for the best possible performance.
Unbuffered Operation
Unbuffered operation reduces power consumption as well as offset error contributed by the external output buffer. The R-2R DAC output is available directly at OUT, allowing 14-bit performance from +VREF to AGND without degradation at zero scale. The DAC's output impedance is also low enough to drive medium loads (RL > 60k) without degradation of INL or DNL; only the gain error is increased by externally loading the DAC output.
MAX544/MAX545
External Output Buffer Amplifier
The requirements on the external output buffer amplifier change whether the DAC is used in unipolar or bipolar operational mode. In unipolar mode, the output amplifier is used in a voltage-follower connection. In bipolar mode (MAX545 only), the amplifier operates with the internal scaling resistors (Figure 2b). In each mode, the DAC's output resistance is constant and is independent of input code; however, the output amplifier's input impedance should still be as high as possible to minimize gain errors. The DAC's output capacitance is also independent of input code, thus simplifying stability requirements on the external amplifier. In bipolar mode, a precision amplifier operating with dual power supplies (such as the MAX400) provides the VREF output range. In single-supply applications, precision amplifiers with input common-mode ranges including AGND are available; however, their output swings do not normally include the negative rail (AGND) without significant degradation of performance. A single-supply op amp, such as the MAX495, is suitable if the application does not use codes near zero. Since the LSBs for a 14-bit DAC are extremely small (152.6V for VREF = 2.5V), pay close attention to the external amplifier's input specification. The input offset voltage can degrade the zero-scale error and might require an output offset trim to maintain full accuracy if the offset voltage is greater than 1/2LSB. Similarly, the input bias current multiplied by the DAC output resistance (typically 6.25k) contributes to zero-scale error. Temperature effects also must be taken into consideration. Over the 0C to +70C commercial temperature range, the offset voltage temperature coefficient (referenced to +25C) must be less than 1.7V/C to add less than 1/2LSB of zero-scale error. The external
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9
+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
amplifier's input resistance forms a resistive divider with the DAC output resistance, which results in a gain error. To contribute less than 1/2LSB of gain error, the input resistance typically must be greater than: 1 1 6.25k / = 205M 2 214 The settling time is affected by the buffer input capacitance, the DAC's output capacitance, and PC board capacitance. The typical DAC output voltage settling time is 1s for a full-scale step. Settling time can be significantly less for smaller step changes. Assuming a single time-constant exponential settling response, a full-scale step takes 10.4 time constants to settle to within 1/2LSB of the final output voltage. The time constant is equal to the DAC output resistance multiplied by the total output capacitance. The DAC output capacitance is typically 10pF. Any additional output capacitance increases the settling time. The external buffer amplifier's gain-bandwidth product is important because it increases the settling time by adding another time constant to the output response. The effective time constant of two cascaded systems, each with a single time-constant response, is approximately the root square sum of the two time constants. The DAC output's time constant is 1s / 10.4 = 96ns, ignoring the effect of additional capacitance. If the time constant of an external amplifier with 1MHz bandwidth is 1 / 2 (1MHz) = 159ns, then the effective time constant of the combined system is: 96ns 2 + 159ns 2 = 186ns )( ) ( This suggests that the settling time to within 1/2LSB of the final output voltage, including the external buffer amplifier, will be approximately 10.4 * 186ns = 1.93s.
Unipolar Configuration
Figure 2a shows the MAX544/MAX545 configured for unipolar operation with an external op amp. The op amp is set for unity gain, and Table 1 lists the codes for this circuit.
Bipolar Configuration
Figure 2b shows the MAX545 configured for bipolar operation with an external op amp. The op amp is set for unity gain with an offset of -1/2VREF. Table 2 shows the offset binary codes for this circuit.
Power-Supply Bypassing and Ground Management
For optimum system performance, use PC boards with separate analog and digital ground planes. Wire-wrap boards are not recommended. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND together at the IC. The best ground connection can be achieved by connecting the DAC's DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC's DGND is connected to the system digital ground, digital noise may get through to the DAC's analog portion. Bypass VDD with a 0.1F ceramic capacitor connected between V DD and AGND. Mount it with short leads close to the device. Ferrite beads can also be used to further isolate the analog and digital power supplies.
Table 1. Unipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 11(00) 1000 0000 0000 00(00) 0000 0000 0000 01(00) 0000 0000 0000 00(00) ANALOG OUTPUT, VOUT VREF * (16,383 / 16,384) VREF * (8192 / 16,384) = 1/2VREF VREF * (1 / 16,384) 0V
Digital Inputs and Interface Logic
The digital interface for the 14-bit DAC is based on a 3-wire standard that is compatible with SPI, QSPI, and MICROWIRE interfaces. The three digital inputs (CS, DIN, and SCLK) load the digital input data serially into the DAC. LDAC (MAX545) updates the DAC output asynchronously. All of the digital inputs include Schmitt-trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX544/MAX545 without additional external logic. The digital inputs are compatible with TTL/CMOS-logic levels.
Table 2. Bipolar Code Table
DAC LATCH CONTENTS MSB LSB 1111 1111 1111 11(00) 1000 0000 0000 01(00) 1000 0000 0000 00(00) 0111 1111 1111 11(00) 0000 0000 0000 00(00) ( ) = Sub-bits ANALOG OUTPUT, VOUT +VREF * (8191 / 8192) +VREF * (1 / 8192) 0V -VREF * (1 / 8192) -VREF * (8192 / 8192) = -VREF
10
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+5V, Serial-Input, Voltage-Output, 14-Bit DACs
Ordering Information (continued)
PART MAX544AEPA MAX544BEPA MAX544AESA MAX544BESA MAX545ACPD MAX545BCPD MAX545ACSD MAX545BCSD MAX545AEPD MAX545BEPD MAX545AESD MAX545BESD MAX545BMJD TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 14 Plastic DIP 14 Plastic DIP 14 SO 14 SO 14 Plastic DIP 14 Plastic DIP 14 SO 14 SO 14 Ceramic SB* INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1
DGND CS DIN SCLK DATA LATCH CONTROL LOGIC SERIAL INPUT REGISTER REF VDD
Functional Diagrams (continued)
MAX544/MAX545
MAX544
14-BIT DAC OUT AGND
*Contact factory for availability.
Chip Information
TRANSISTOR COUNT: 2209
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11
+5V, Serial-Input, Voltage-Output, 14-Bit DACs MAX544/MAX545
________________________________________________________Package Information
SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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